tinyVTA is a high-performance FPGA-based tensor accelerator designed for deep neural network inference. It features optimized block matrix-multiply-accumulate (MMAC) and activation function (ACTIV) kernels, implemented using Vitis HLS and invoked through a custom instruction set architecture (ISA). The project includes a custom Pythonic compiler (tinyTVM) that translates PyTorch and TensorFlow fully connected neural network models into tinyVTA executable instructions. It utilizes the Pynq API for memory management via PynqBuffer objects and PS/PL interfacing with AXI4 protocols. Additionally, APIs are created using Tornado, enabling any client to compile their DNN models, remotely program a supported FPGA connected to a server, and perform ML inference through remote procedure calls. The accelerator was evaluated on the Xilinx UltraScale+ ZCU104 FPGA with a fully connected neural network for MNIST digit recognition, achieving precise hardware-software output consistency through extensive verification with a software testbench and hardware validation.
This project presents a native implementation of the Signal Protocol for secure end-to-end messaging, using the cryptography library in Python. The project includes the development of a secure messaging application with a simple client-side GUI created using PySide6 and a WebSocket-based messaging system utilizing socketio. The server adheres to the Signal Protocol Specification, storing only credentials and public keys, receiving only ciphertext, and enabling multiple concurrent two-way communications. The client application allows users to select chat partners and locally persist chat messages, enabling local chat history. For the Signal Protocol implementation, the Extended Triple Diffie-Hellman (X3DH) key agreement protocol and the Double Ratchet Algorithm were employed. The X3DH protocol facilitates the establishment of a shared secret key between two parties using their respective public keys, ensuring forward secrecy and cryptographic deniability. The Double Ratchet Algorithm was implemented to provide secure and synchronized key exchanges for continued communication. The server uses TinyDB to store client information and acts as a communication conduit between clients without retaining any messages. The client-side application features a user-friendly interface for authentication, logging in, selecting chat partners, and viewing chat history. This project demonstrates the practical application of secure messaging protocols and provides a robust foundation for further development in secure communication systems.
This project introduces a unique implementation of Deep Recurrent Q-Learning (DRQL) tailored for Partially Observable Markov Decision Processes (POMDPs). Our approach incorporates transfer learning for feature extraction, utilizes a customized LSTM for temporal recurrence, and introduces a domain-informed reward function to expedite convergence compared to the vanilla implementation outlined in the original paper. The performance evaluation centers on two adaptive Atari 2600 games: Assault-v5 and Bowling, where game difficulty scales with player proficiency. A comparative analysis of the convergence of our optimized reward function and the vanilla version is conducted, employing StepLR and CosineAnnealingLR learning-rate schedulers, complemented by theoretical explanations. Additionally, we propose an efficient windowed episodic memory implementation that optimizes GPU memory utilization through bootstrapped sequential updates.
Implemented Deep Neural Network architectures using PyTorch for advanced machine learning applications. The repository contains two major projects. The first project involves creating a Long Short-Term Memory (LSTM)-based Algorithmic Stock Trader, utilizing the S&P 500 stock-market ticker dataset. The implementation includes modeling time series with LSTM, experimenting with techniques such as normalization and feature engineering, and assessing the algorithmic trading module’s profitability under various conditions such as bid-ask spread and commissions. The second project focuses on Facial Similarity Metric Learning and Face Generation using Deep Convolutional Generative Adversarial Networks (DCGAN) with the Labeled Faces in the Wild dataset. This project employs a transfer-learned, ResNet-based Siamese Network for Similarity Metric Learning, along with experiments involving regularization, learning-rate scheduling, dropout, and optimization variations. The DCGAN is trained to generate new faces and modified into a Conditional GAN to generate unseen images based on a given input image from the Siamese Network.
This repository presents implementations of various compiler optimizations and infrastructure for MiniJava, a Java subset, using JavaCC and JTB. The projects include a type checker, function inliner with Rapid Type Analysis, a register allocator utilizing Kempe’s graph coloring heuristic, and a for-loop parallelization employing the GCD test. Each implementation is accompanied by a detailed problem specification. For the Type Checker project, a Java-like object-oriented language is type-checked using a provided grammar file, and detailed error reporting is implemented. The Function Inliner focuses on determining inlineability based on RTA and transforming method calls. Register Allocation involves spilling variables to memory using liveness analysis results. Loop Parallelization utilizes the GCD test to identify parallelizable for-loops in methods, marked with the /* @Parallel */ decorator.
This project explores High-Level Synthesis using Algorithmic Assembly (AA), an Intermediate Representation (IR) for the AHIRv2 C-to-VHDL compiler developed at IIT Bombay. The first part involves the design of a Shift-and-Add Multiplier and a Shift-and-Subtract Divider Circuit using Algorithmic Assembly. The second part focuses on the hardware acceleration of matrix multiplication using loop optimizations and parallelism in Algorithmic Assembly, providing practical insights into the translation of algorithms to hardware while leveraging the capabilities of Algorithmic Assembly.
Developed the application’s backend using Flask, a powerful web framework in Python. Utilized Python programming language to implement robust and efficient backend functionalities, including user authentication, database management, and secure file access. Implemented a secure login system using CSRF tokens to prevent cross-site request forgery attacks. Employed industry best practices to ensure the confidentiality and integrity of user credentials and session management. Incorporated the Chinese Wall Model for temporal access control of documents within the application. Designed a comprehensive database structure to manage users, companies, and files, enforcing strict access restrictions based on user roles and conflict of interest criteria.
This project conducts the formal verification of a given Ripple Carry Adder (RCA) implementation. Binary Decision Diagrams (BDDs) were employed using bddlib to represent the provided RTL description of the adder circuit. Additionally, BDD operations, including Image and Pre-Image, were implemented natively in C++ to rigorously prove critical properties such as Goldberg’s Conjecture, ensuring the correctness of the adder’s design implementation. Furthermore, SAT solvers were used to construct the smallest spanning test-vector set for post-fabrication physical design testing, thereby enhancing the circuit’s reliability and robustness.
This project involved the development of an embedded system for autonomous valet-parking. This involved the model-based design of a finite state automaton using the heptagon/BZR modeling language to synthesize a highly optimized, easily verifiable reactive kernel. At the hardware level, we engineered sensor and actuator interfacing drivers for the Atmega328p microcontroller, coupled with real-time operating system (RTOS) features like scheduling, interrupt handling, and memory management, resulting in enhanced system responsiveness and performance. Additionally, we designed and fine-tuned native algorithms for obstacle wall-hugging, PID line following, track color inversion, and parking space identification to ensure seamless integration into our embedded system.
In the realm of Very Large Scale Integration (VLSI), characterized by digital circuits comprising billions of transistors, the demand for computerized design automation, design verification, and testing algorithms is paramount. Digital circuits are typically represented as graphs, where logic gates serve as nodes, and their interconnections form the edges. Given the complexity of VLSI circuits, often involving millions of logic gates, a pressing need arises for swift and highly optimized graph algorithms. While optimized graph libraries such as NetworkX exist, there is a noticeable gap in the availability of open-source libraries tailored specifically to the VLSI computer-aided design automation industry. In this project, a range of optimized algorithms and implementations were initially developed, including the Lee Algorithm, Kruskal’s Algorithm, Binary Decision Diagrams, Bellman-Ford Algorithm, Prim’s Algorithm, Dijkstra’s Algorithm, Compiled Code Simulator, and Event-Driven Simulator. These implementations were meticulously documented for transparency and accessibility. To enhance performance, optimization tools such as Numba were employed to accelerate these algorithms, with systematic comparisons made against Pythonic and other conventional implementations. Furthermore, Automan was utilized to streamline simulations, benchmark algorithms, and evaluate results across a diverse range of circuits and graphs, each varying in size and complexity. This project underscores a dedicated commitment to advancing the field of VLSI design by offering optimized algorithms and leveraging cutting-edge tools to meet the specific demands of the VLSI CAD industry.
This project showcases an optimized Numba-JIT accelerated Pythonic implementation of the Kohonen Self-Organizing Map (SOM) with customizable grid matrix sizes, designed for multispectral satellite image processing. The system takes multispectral satellite images as input and generates coded images using the trained SOM as a codebook, all conveniently packaged as a Python executable. Furthermore, the project includes image restoration capabilities, enabling a comparison with the original image, and provides vivid data visualization through informative plots. The implementation allows users to set parameters such as the SOM dimensions, initial learning rate, maximum iterations, and neighborhood function spread factor for fine-tuned control during execution.
An IoT-based monitoring system for a biogas plant that measures and displays parameters such as gas concentrations, humidity, and temperature. The design consists of a tailor-made, custom-designed, two-layer printed circuit board interfacing with gas sensors in a modular fashion using I2C. The data is sent to a central server and stored in a cloud database for remote access and analysis through a web application. The system helps optimize biogas production, identify issues, improve safety, and offers the flexibility to integrate additional gas sensors. Furthermore, we successfully addressed anticipated problems during the development and prototyping stages and submitted a complete, market-ready product.
This project was recognized with the Best Project Award for Electronics Design Lab at IIT Bombay.
The IITB-RISC-22, a 16-bit computer system, boasts a remarkable Turing-complete ISA capable of executing 17 instructions and featuring 8 general-purpose registers (R0 to R7), with R7 doubling as the program counter. The architecture also incorporates a carry flag and a zero flag, along with two 16-bit Arithmetic Logic Units (ALUs) and a 16-bit priority encoder providing a 16-bit output and a 3-bit register address. The system further encompasses two Sign Extenders, SE6 and SE9, tailored for 6- and 9-bit inputs, respectively, yielding 16-bit outputs. Complementing these, there are two left bit shifters, Lshifter7 and Lshifter1, which respectively perform left shifts of 7 and 1 bit, appending zeros to the right and resulting in 16-bit outputs. Additionally, the architecture includes four temporary registers, TA, TB, TC, and TD, where TA, TB, and TC are 16-bit, and TD is 3-bit. This comprehensive design is complemented by a 128-byte (64-word-addressable) random-access memory.
In a significant development effort, a six-stage pipelined version of the processor was meticulously crafted. The entire instruction set was rigorously tested by loading it into memory, and waveforms were verified on the Xilinx Spartan-6 FPGA. To elevate processor performance, the ALU operations were expanded to encompass a two-way-fetch out-of-order superscalar architecture, boosting instructions-per-cycle (IPC) rates. This enhancement introduced a reorder buffer, a reservation station, and an implementation of Tomasulo’s register-renaming algorithm, thereby streamlining the processor’s execution and optimizing its overall efficiency.
This project involved the development of a UDP-based Stop-and-Wait algorithm for reliable data transfer. The sender created UDP sockets for communication with the receiver. It meticulously managed packet transmission and retransmission based on acknowledgments from the receiver, ensuring data integrity. The code featured a sophisticated timeout mechanism, utilizing the select() function for precise timeout management. This approach enabled the sender to monitor responses and handle packet loss scenarios effectively. On the receiver side, the system continuously listened for incoming packets. It introduced a probabilistic packet drop simulation mechanism, where packets were randomly dropped based on a user-defined probability, enabling the examination of the protocol’s robustness in the face of potential data loss. The receiver meticulously tracked the sequence numbers of incoming packets, allowing it to acknowledge correctly received packets and request retransmissions when necessary. This project delved into the intricacies of network communication, demonstrating the implementation of a reliable communication protocol with advanced timeout handling and packet loss simulation.
Recognizing that VLSI design schematics often exceed the capacity of a single FPGA due to the finite number of programmable logic elements, this project adopts a graph-based approach to represent interconnections between circuit elements. Logic gates, LUTs, FFs, and other design entities were seamlessly modeled as graph nodes, while interconnections were depicted as edges. In cases involving multiple parallel interconnects, weighted graphs were employed for precision. This method facilitated the automation of dividing the design among multiple FPGAs using CAD, effectively transforming the challenge into a graph partitioning problem. This project implements three significant partitioning algorithms—Kernighan-Lin, Clustering-Based, and Hagen-Kahng-EIG—using Python, meticulously identifying metrics to assess their performance and prioritize the minimization of FPGA interconnects. Leveraging co-optimization across these metrics, advanced cost functions were developed, demonstrating the project’s commitment to achieving optimal circuit partitioning solutions within the realm of VLSI CAD.
This project involves an optimized Multiply-Accumulate Circuit, implemented using VHDL with a Dadda Multiplier Architecture and a 16-bit Brent-Kung Adder. It effectively multiplies two 8-bit operands and adds a 16-bit number to the product. The hardware descriptions were tested, and their simulation was executed using GHDL, offering comprehensive test reports. The submission encompasses all necessary files, including test scripts and waveform analysis tools. Detailed results and RTL synthesis for the FPGA were performed using Intel Quartus.
In this study, the project embarked on leveraging deep learning to address image colorization and noise reduction challenges. The centerpiece of this project was the deployment of a Convolutional Neural Network (CNN)-based autoencoder, meticulously trained on grayscale CIFAR-10 images, achieving a Root Mean Square Error (RMSE) score of 0.052 for generating colorized versions. Further investigations encompassed a comparative analysis of the performance of autoencoders and Principal Component Analysis (PCA) in the context of Gaussian and salt-and-pepper noise reduction, employing training data from MNIST images. This analytical approach provided valuable insights into the strengths and limitations of these methodologies, shedding light on the suitability of various noise reduction scenarios. Additionally, the project ventured into exploring the data specificity of autoencoders by executing the same model on different image classes, effectively illustrating how autoencoders adapt to diverse datasets.