IITB-RISC-2022
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The IITB-RISC-22, a 16-bit computer system, boasts a remarkable Turing-complete ISA capable of executing 17 instructions and featuring 8 general-purpose registers (R0 to R7), with R7 doubling as the program counter. The architecture also incorporates a carry flag and a zero flag, along with two 16-bit Arithmetic Logic Units (ALUs) and a 16-bit priority encoder providing a 16-bit output and a 3-bit register address. The system further encompasses two Sign Extenders, SE6 and SE9, tailored for 6- and 9-bit inputs, respectively, yielding 16-bit outputs. Complementing these, there are two left bit shifters, Lshifter7 and Lshifter1, which respectively perform left shifts of 7 and 1 bit, appending zeros to the right and resulting in 16-bit outputs. Additionally, the architecture includes four temporary registers, TA, TB, TC, and TD, where TA, TB, and TC are 16-bit, and TD is 3-bit. This comprehensive design is complemented by a 128-byte (64-word-addressable) random-access memory.
In a significant development effort, a six-stage pipelined version of the processor was meticulously crafted. The entire instruction set was rigorously tested by loading it into memory, and waveforms were verified on the Xilinx Spartan-6 FPGA. To elevate processor performance, the ALU operations were expanded to encompass a two-way-fetch out-of-order superscalar architecture, boosting instructions-per-cycle (IPC) rates. This enhancement introduced a reorder buffer, a reservation station, and an implementation of Tomasulo’s register-renaming algorithm, thereby streamlining the processor’s execution and optimizing its overall efficiency.