High-Level Synthesis using Algorithmic Assembly
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This project explores High-Level Synthesis using Algorithmic Assembly (AA), an Intermediate Representation (IR) for the AHIRv2 C to VHDL compiler developed at IIT Bombay. The first part involves the design of a Shift and Add Multiplier and a Shift and Subtract Divider Circuit using Algorithmic Assembly. The second part focuses on the Hardware Acceleration of Matrix Multiplication using Loop Optimizations and Parallelism in Algorithmic Assembly providing practical insights into the translation of algorithms to hardware, leveraging the capabilities of Algorithmic Assembly.