Implementation, Visualisation and Analysis of Circuit Partitioning Algorithms
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Recognizing that VLSI design schematics often exceed the capacity of a single FPGA due to the finite number of programmable logic elements, this project adopts a graph-based approach to represent interconnections between circuit elements. Logic gates, LUTs, FFs, and other design entities were seamlessly modeled as graph nodes, while interconnections were depicted as edges. In cases involving multiple parallel interconnects, weighted graphs were employed for precision. This method facilitated the automation of dividing the design among multiple FPGAs using CAD, effectively transforming the challenge into a graph partitioning problem. This project implements three significant partitioning algorithms Kernighan-Lin, Clustering-Based, and Hagen-Kahng-EIG – using Python, meticulously identifying metrics to assess their performance and prioritize the minimization of FPGA interconnects. Leveraging co-optimization across these metrics, advanced cost functions were developed, demonstrating the project’s commitment to achieving optimal circuit partitioning solutions within the realm of VLSI CAD.