Optimised Multiply Accumulate Circuit using Dadda Multiplier Architecture
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This project involves an optimized Multiply Accumulate Circuit, implemented using VHDL with a Dadda Multiplier Architecture and a 16-bit Brent Kung Adder. It effectively multiplies two 8-bit operands and adds a 16-bit number to the product. The hardware descriptions were tested and their simulation was executed using GHDL, offering comprehensive test reports. The submission encompasses all necessary files, including test scripts and waveform analysis tools. Detailed results and RTL synthesis for FPGA was performed using Intel Quartus