This project introduces a unique implementation of Deep Recurrent Q-Learning (DRQL) tailored for Partially Observable Markov Decision Processes (POMDPs). Our approach incorporates Transfer Learning for feature extraction, utilizes a customized LSTM for temporal recurrence, and introduces a domain-informed reward function to expedite convergence compared to the vanilla implementation outlined in the original paper. The performance evaluation centers around two adaptive Atari 2600 games: Assault-v5 and Bowling, where game difficulty scales with player proficiency. Comparative analysis between the convergence of our optimized reward function and the vanilla version is conducted, employing StepLR and CosineAnnealingLR learning rate schedulers, complemented by theoretical explanations. Additionally, we propose an efficient windowed episodic memory implementation that optimizes GPU memory utilization through bootstrapped sequential updates.
Implemented Deep Neural Network architectures using PyTorch for advanced machine learning applications. The repository contains two major projects. The first project involves creating a Long-Short-Term-Memory (LSTM) based Algorithmic Stock Trader, utilizing the sp500 stock market tickers dataset. The implementation includes modeling time series with LSTM, experimenting with techniques like normalization and feature engineering, and assessing the algorithmic trading module’s profitability under various conditions such as buy-ask spread and commissions. The second project focuses on Facial Similarity Metric Learning and Face Generation using Deep Convolutional Generative Adversarial Networks (DCGAN) with the Labeled Faces in the Wild dataset. This project employs a Transfer Learned ResNet based Siamese Network for Similarity Metric Learning, along with experiments involving regularization, learning rate scheduling, dropout, and optimization variations. The DCGAN is trained to generate new faces and modified into a Conditional GAN to generate unseen images based on a given input image from the Siamese Network.
This repository presents implementations of various compiler optimizations and infrastructure for MiniJava, a Java subset, using JavaCC and JTB. The projects include a type checker, function inliner with Rapid Type Analysis, a register allocator utilizing Kempe’s graph coloring heuristic, and a for-loop parallelization employing the GCD test. Each implementation is accompanied by a detailed problem specification. For the Type Checker project, a Java-like object-oriented language is type-checked using a provided grammar file, and detailed error reporting is implemented. The Function Inliner focuses on determining inlineability based on RTA and transforming method calls. Register Allocation involves spilling variables to memory using liveness analysis results. Loop Parallelization utilizes the GCD test to identify parallelizable for-loops in methods, marked with the /* @Parallel */ decorator.
This project explores High-Level Synthesis using Algorithmic Assembly (AA), an Intermediate Representation (IR) for the AHIRv2 C to VHDL compiler developed at IIT Bombay. The first part involves the design of a Shift and Add Multiplier and a Shift and Subtract Divider Circuit using Algorithmic Assembly. The second part focuses on the Hardware Acceleration of Matrix Multiplication using Loop Optimizations and Parallelism in Algorithmic Assembly providing practical insights into the translation of algorithms to hardware, leveraging the capabilities of Algorithmic Assembly.
Developed the application’s backend using Flask, a powerful web framework in Python. Utilized Python programming language to implement robust and efficient backend functionalities, including user authentication, database management, and secure file access. Implemented a secure login system using CSRF tokens to prevent cross-site request forgery attacks. Employed industry best practices to ensure the confidentiality and integrity of user credentials and session management. Incorporated the Chinese Wall Model for temporal access control of documents within the application. Designed a comprehensive database structure to manage users, companies, and files, enforcing strict access restrictions based on user roles and conflict of interest criteria.
This project conducts the formal verification of a given Ripple Carry Adder (RCA) implementation, Binary Decision Diagrams (BDDs) were employed using bddlib to represent the provided RTL description of the adder circuit. Additionally, BDD operations, including Image and Pre-Image, were implemented natively in C++ to rigorously prove critical properties such as Goldberg’s Conjecture, ensuring the correctness of the adder’s design implementation. Furthermore, SAT solvers were used to construct the smallest spanning test-vector set for post-fabrication physical design testing, thereby enhancing the circuit’s reliability and robustness.
This project involved the development of an embedded system for autonomous valet-parking. This involved the model-based design of a finite state automaton using the heptagon/BZR modeling language to synthesize a highly optimized, easily verifiable reactive kernel. At the hardware level, we engineered sensor and actuator interfacing drivers for the Atmega328p microcontroller, coupled with real-time operating system (RTOS) features like scheduling, interrupt handling, and memory management, resulting in enhanced system responsiveness and performance. Additionally, we designed and fine-tuned native algorithms for obstacle wall-hugging, PID line following, track color inversion, and parking space identification to ensure seamless integration into our embedded system.
In the realm of Very Large Scale Integration (VLSI), characterized by digital circuits comprising billions of transistors, the demand for computerized design automation, design verification, and testing algorithms is paramount. Digital circuits are typically represented as graphs, where logic gates serve as nodes, and their interconnections form the edges. Given the complexity of VLSI circuits, often involving millions of logic gates, a pressing need arises for swift and highly optimized graph algorithms. While existing optimized graph libraries like networkx exist, there is a noticeable gap in the availability of open-source libraries tailored specifically to the VLSI computer-aided design automation industry. In this project, a range of optimized algorithms and implementations were initially developed, including the Lee Algorithm, Kruskal’s Algorithm, Binary Decision Diagrams, Bellman-Ford Algorithm, Prim Algorithm, Dijkstra’s Algorithm, Compiled Code Simulator, and Event Driven Simulator. These implementations were meticulously documented for transparency and accessibility. To enhance performance, optimization tools such as Numba were employed to accelerate these algorithms, with systematic comparisons made against Pythonic and other conventional implementations. Furthermore, Automan was utilized to streamline simulations, benchmark algorithms, and evaluate results across a diverse range of circuits and graphs, each varying in size and complexity. This project underscores a dedicated commitment to advancing the field of VLSI design by offering optimized algorithms and leveraging cutting-edge tools to meet the specific demands of the VLSI CAD industry.
This project showcases an optimized Numba-JIT accelerated Pythonic implementation of the Kohonen Self-Organizing Map (SOM) with customizable grid matrix sizes, designed for multispectral satellite image processing. The system takes multispectral satellite images as input and generates coded images using the trained SOM as a codebook, all conveniently packaged as a Python executable. Furthermore, the project includes image restoration capabilities, enabling a comparison with the original image, and provides vivid data visualization through informative plots. The implementation allows users to set parameters such as the SOM dimensions, initial learning rate, maximum iterations, and neighborhood function spread factor for fine-tuned control during execution.
An IoT-based monitoring system for a biogas plant that measures and displays parameters such as gas concentrations, humidity, and temperature. The design consists of a tailor-made custom in-house designed two-layer printed circuit board interfacing gas sensors in a modular fashion using I2C. The data is sent to a central server and stored in a cloud database for remote access and analysis through a web application. The system helps optimize biogas production, identify issues, improve safety, and offers flexibility to integrate additional gas sensors. Furthermore, we successfully addressed anticipated problems during development and prototyping stages and submitted a complete market-ready product
This project was recognised with Best Project Award for Electronics Design Lab at IIT Bombay
